Various types of shift registers have been used. One of the most basic, conventional shift registers comprises a plurality of cascaded D flip-flops. A shift register of this type, however, disadvantageously occupies a substantially large area on a substrate when it is constructed in an integrated circuit form, because the number of components of each D flip-flop and the number of components of associated circuits are large.
In Japanese Published Patent Application No. SHO 63-76198, K. Akiyama discloses a shift register of the type which does not use any D flip-flops. The shift register of this type comprises a plurality of 1-bit memory cells adjacent ones of which are interconnected by two MOS transistors which are ON-OFF controlled by control signals. Each of the 1-bit memory cells comprises two inverters which are connected in a ring configuration with two MOS transistors disposed between the respective inputs and the respective outputs of the inverters. The two MOS transistors in the ring are ON-OFF controlled by control signals applied to the respective gate electrodes, which control signals are different from the control signals used to ON-OFF control the MOS transistors interconnecting adjacent memory cells. This type of shift register is more advantageous than shift registers using D flip-flops when they are formed as integrated circuits because the number of circuit components is smaller. According to the statement in this Japanese application, this shift register is free of a race condition. A "race condition" is an undesirable phenomenon in which, during a clock period for shifting one bit, plural bits of data are shifted through a shift register. However, in the shift register of Akiyama, due to time delays imparted by two inverters in the paths of the control signals, two of the control signals applied through two respective gates therefor, which should be in opposite phase with each other, would become in phase with each other for a short time period. This causes an undesirable race condition.
A second type of shift register that does not employ D flip-flops includes latching sections each comprising a series combination of two inverters and a CMOS transmission gate connected in parallel with the series combination of the two inverters, and shifting sections each comprising a CMOS transmission gate connecting two latching sections. In this second type of shift register, data is shifted therethrough by clocking the CMOS transmission gates of the latching and shifting sections, simultaneously. However, this simultaneous clocking could cause a race condition.
Accordingly, an object of the present invention is to provide a novel shift register which includes a relatively small number of circuit components and, hence, is suitable for constructing in an integrated circuit form, and which is free of a race condition and, therefore, can operate with stability and precision.